1. Field of the Invention
The present invention relates to a semiconductor memory device, and more specifically, to a semiconductor memory device suitable for mounting mixed with a logic circuit such as a logic device and a microprocessor. More specifically, the present invention relates to a configuration of a semiconductor memory device for reducing cycle time in a reading operation of a DRAM (Dynamic Random Access Memory) mounted together with logic circuitry.
2. Description of the Background Art
DRAM system LSI (Large Scale Integrated Circuit Device) having a DRAM and a logic device or a microprocessor integrated on one same semiconductor substrate has come to be widely used. The DRAM embedded system LSI is advantageous over the conventional system in which separate DRAM and logic device are soldered on a printed circuit board in the following points.
(1) Consideration of pin terminals of the separate DRAM is unnecessary, and therefore data bus width between the DRAM and the logic can be widened, which leads to improved data transfer rate and hence improved system performance; PA1 (2) A data bus formed on a semiconductor substrate has smaller parasitic capacitance as compared with a line on a printed board, and therefore charging/discharging current of signal line can be reduced, which leads to smaller current consumption at the time of data transfer; and PA1 (3) Single packaging becomes possible, and data bus lines and control signal lines on the printed board can be reduced, so that occupation area on the printed board can be reduced.
FIG. 19 represents an example of a conventional DRAM embedded system LSI configuration.
Referring to FIG. 19, in the DRAM embedded system LSI, a logic circuit LG and a DRAM macro are integrated on one semiconductor substrate chip CH.
The DRAM macro includes memory arrays MA0 and MA1 each having a plurality of memory cells arranged in a matrix of rows and columns, row decode circuits XD0 and XD1 provided for memory arrays MA0 and MA1, respectively, for selecting an address-designated row of the corresponding memory arrays MA0 and MA1, column decode circuits YD0 and YD1 provided for memory arrays MA0 and MA1, respectively, for selecting an address-designated column of memory arrays MA0 and MA1, data paths DP0 and DP1 for communicating data with the column of memory cells selected by column decode circuits YD0 and YD1, and a control circuit CG controlling data access operation to memory arrays MA0 and MA1.
Data paths DP0 and DP1 are coupled to logic circuit LG through data buses DB0 and DB1, and control circuit CG is coupled to logic circuit LG through a control bus CTB. In FIG. 19, data buses DB0 and DB1 transmit 128 bits of write data and 128 bits of read data separately.
FIG. 20 is a schematic representation of the configurations of memory arrays MA0 and MA1 shown in FIG. 19. Memory arrays MA0 and MA1 are generally represented as one memory array MA in FIG. 20, as the memory arrays have identical configurations.
Memory array MA includes a plurality of memory cell blocks MCB arranged in a matrix of rows and columns. Though not explicitly shown, memory cells are arranged in a matrix of rows and columns in memory cell block MCB. For each memory cell block MCB, local IO line pairs LIOs for communicating data with the corresponding memory cell block are provided. The pair of local IO lines transmit signals complementary to each other.
Sense amplifier groups SAs are arranged corresponding to respective memory cell blocks MCB. Sense amplifier groups SAs have shared sense amplifier scheme, and shared by memory cell blocks adjacent in the column direction. The sense amplifier groups SAs include sense amplifier circuits SA each provided corresponding to each column of the corresponding memory cell block, for sensing, amplifying and latching data of the address-designated memory cell column when activated. Sense amplifier groups SAs are selectively coupled to the corresponding local IO line pairs LIOs.
Word lines WLs are arranged commonly to memory cell blocks MCB arranged aligned in the row direction. In operation, one word line WL among word lines belonging to one row block (a block consisting of a plurality of memory cell blocks arranged aligned in the row direction) is driven to the selected state.
In an area between memory cell blocks adjacent to each other in the row direction and the area outside the memory cell blocks (these areas will be referred to as interblock areas), global IO line pairs GIO0 to GIO127 are arranged extending in the column direction. Four global IO line pairs are arranged commonly to memory cell blocks aligned in the column direction. Four pairs of local IO lines LIOs are arranged for each memory cell block, and four pairs of local IO lines LIOs provided corresponding to each memory cell block MCB in one row block are each coupled to the corresponding global IO line pair through an IO switch IOSW.
Each of the global IO line pairs GIO0 to GIO127 transmits mutually complementary signals, and coupled to a data path shown in FIG. 19 and coupled to logic circuit LG through a read/write circuit in the data path.
In the same interconnection layer as global IO line pairs GIO0 to GIO127, a column selection line CSL is arranged extending in the column direction over memory array MA. Column selection lines CSLs are shared by memory cell blocks MCB arranged aligned in the column direction. By IO switch IOSW, local IO line pairs LIOs of the selected row block are coupled to global IO line pairs GIO0 to GIO127, and local IO line pairs LIOs of nonselected row blocks are separated from global IO line pairs GIO0 to GIO127. Therefore, four columns are simultaneously selected in each column block (a block constituted by memory block cell blocks arranged aligned in the column direction), and four local IO line pairs LIOs are coupled to the corresponding global IO line pairs.
FIG. 21 is a block diagram representing arrangements of circuits and flow of control signals related to a reading operation in a conventional DRAM macro.
Referring to FIG. 21, difference in access time between data reading from a memory cell connected to a sense amplifier SAf positioned at a farthest point from a control circuit and data reading from a memory cell connected to a sense amplifier SAn positioned at the nearest point on the memory array will be considered.
The sense amplifier SAf at the farthest point is coupled selectively to local IO line pair LIOf by column selection line CSLf, and data read to local IO line pair LIOf is transmitted to the corresponding global IO line pair GIOf. Potential difference generated on global IO line pair GIOf because of the coupling with sense amplifier SAf is amplified by preamplifier PAf, and read data is taken out.
Similarly, the sense amplifier SAn at the nearest point is selectively coupled through local IO line pair LIOn to global IO line pair GIOn, by column selection line CSLn. Potential difference generated on global IO line pair GIOn because of the coupling with sense amplifier SAn is amplified by preamplifier PAn and the read data is taken out.
In the following, signal lines, control signals and circuits having reference characters with a suffix "f" in the specification represent those provided corresponding to the sense amplifier SAf at the farthest point. Similarly, those designated by reference characters with suffix "n" represent those provided corresponding to the sense amplifier SAn at the nearest point.
Control signal CG takes in a read command and an address in synchronization with an external clock in a reading operation, and generates an equalize signal GIOEQ to cause precharge/equalize operation on global IO line pair, a preamplifier activating signal PAE designating activation timing of preamplifier PA, and read predecode signals YA &lt;3:0&gt; and YB &lt;3:0&gt; input to the column decoder. Here, each of the read predecode signals YA &lt;3:0&gt; and YB &lt;3:0&gt; is a signal generated by a logical product operation between a signal obtained by predecoding two bits of the column address and a control signal CDE determining activation timing of the column selection line. Each column decoder YD selects one of sixteen sense amplifiers arranged corresponding to each memory cell block, in accordance with the read predecode signals YA &lt;3:0&gt; and YB &lt;3:0&gt;.
The column selection line CSLf corresponding to the sense amplifier SAf at the farthest point is driven by column decoder YDf, and column selection line CSLn corresponding to the sense amplifier SAn at the nearest point is driven by column decoder YDn.
Here, line delays of signals GIOEQ, PAE, YA and YB will be represented as .DELTA.tGIOEQ, .DELTA.tPAE, .DELTA.tY and .DELTA.tY. For simplicity of description, it is assumed that the line delays are equal to each other. As these signals are propagated in one direction, relative relations between each of the signals is constant, when each position of the preamplifier on the data path is used as a reference. Therefore, by considering timings of change of various signals related to the reading operation with the positions of respective preamplifiers used as reference, the influence of delays .DELTA.tGIOEQ, .DELTA.tPAE, .DELTA.tY and .DELTA.tY can be eliminated.
FIG. 22 is a timing chart representing a problem in a reading operation of a conventional DRAM macro.
Referring to FIG. 22, VCSLn and VGIOn represent variation in potential level on column selection line CSLn and variation in potential difference generated on global IO line pair GIOn at the position of preamplifier PAn. Similarly, VCSLf and VGIOf represent variation in potential level of column selection line CSLf and variation in potential difference generated on global IO line pair GIOf at the position of preamplifier PAf. Further, as already described, preamplifier activating signal PAE and equalize signal GIOEQ are propagated in the same direction as read predecode signals YA &lt;3:0&gt; and YB &lt;3:0&gt;. Therefore, variations in potential levels of preamplifier activating signal PAE and equalize signal GIOEQ at respective preamplifier positions can be represented by the same timing relative to the timing when the corresponding column decoder drives the column selection line as a reference.
The time t0 is the timing when column decoder YDn outputs a column selection signal to column selection line CSLn for column selection line CSLn and global IO line pair GIOn, and the timing when column decoder YDf generates a column selection signal to column selection line CSLf for column selection line CSLf and global IO line pair GIOf. By the time t0 when the corresponding column selection line CSL is activated, equalize operation for each global IO line pair is completed, and global IO line equalize signal GIOEQ is inactivated.
At the sense amplifier SAn at the nearest point, the distance between sense amplifier SAn and column decoder YDn driving column selection line CSLn is short. Therefore, the data amplified by the sense amplifier is transmitted to global IO line pair GIOn starting from time t0.
Potential difference generated on global IO line pair GIOn attains to a preamplifier sensitivity (200 mV in FIG. 22) at time t2 after necessary time period tRE for amplifying read data on global IO line from time point t0, and it becomes possible to establish or define the read data.
As for the sense amplifier SAf at the farthest point, line delay .DELTA.tCSL over column selection line CSLf from column decoder YDf to sense amplifier SAf is innegligible. Further, the data read from sense amplifier SAf after activation by column selection line CSLf is transmitted over global IO line pair GIOf with line delay .DELTA.tGIO in a direction opposite to the direction of signal propagation over column selection line. Therefore, an innegligible line delay results because of the sum of these. In FIG. 22, the sum of line delays is represented as .DELTA.tCSL+.DELTA.tGIO.
Therefore, VGIOf exceeds the preamplifier sensitivity at time point t4 after tRE from time point t1.
When preamplifier PAn is activated by preamplifier activating signal PAE from the time point t4, it becomes possible to take out the data read from the memory cell connected to sense amplifier SAn at the nearest point at time point t6 after the lapse of preamplifier activating period tPAE necessary for the data to be established after the activation of the preamplifier. After reading the read data and the read data is established, the global IO line pair is equalized and initialized to the precharge potential, and thus at time t7 after the equalizing period tEQ from the time point t6, one read cycle for the memory cell connected to SAf at the farthest point is completed.
In this manner, when an access is made to the memory cell connected to the sense amplifier SAf at the farthest point, the time point when the read data appears on the global IO line pair at the position of the preamplifier is delayed by .DELTA.tCSL+.DELTA.tGIO from the time when an access is made to the memory cell connected to the sense amplifier SAn at the nearest point.
Therefore, the time for activating the preamplifiers and the start of equalization of the global IO line pair must be so set as to accommodate the access to the memory cell connected to the sense amplifier SAf at the farthest point. Therefore, the minimum read cycle time in the conventional DRAM macro is .DELTA.tCSL+.DELTA.tGIO+tRE+tPAE+tEQ.
As described above, in the conventional configuration, it has been necessary to define as the minimum read cycle time the time period including line delay caused by the column selection line and the global IO line pair, which hinders increase in speed of operation.